Multi-Chambered Planar Magnetics Design Techniques

Because the reluctance of the upper and lower air gaps is much larger than those posed by the inner and outer material paths of the core structure, flux produced by the MMF of the

transformer section of the PIM is restricted primarily to the inside sections of the core system. Therefore, PIM inductive and transformer-related operations will be largely

independent, with insignificant magnetic interaction. This situation also implies that there are no significant restrictions on turn ratios between transformer and inductor windings,

whereas in some IM converter designs [2], such restrictions are required to insure proportionality of winding driving potentials in order to permit their magnetic components to

utilize a common core structure.

In the cross-sectional view of the PIM construction in Fig. 5, the unshaded areas on the outside “walls” of the core structure represent open parts of the core for accessing the

ends of the PCB windings located in each chamber. Fig. 6 shows the overall construction approaches for viable PIM assemblies of the “stacked” variety [7][8], with typical access locations for PCB winding terminations illustrated.

Another PIM construction alternative is a “side-by-side” arrangement of transformer and inductive windings [9] as depicted in Fig. 7. In contrast to the design of Fig. 3, the inductive portion of the PIM lies in the center of the structure that surrounds the center portion. The core “wall” that separates the two “chambers” of the core system PCB Assembly then serves as a common flux path for inductive and transformer operations. Fig. 8 is a sketch of a practical implementation ofthe PIM concept [9] of Fig. 7, and a cross-sectional view of the design is shown in Fig. 9.

As indicated in Fig. 9, interactions between the magnetic operations of the system can be minimized further by the presence of a small air chamber placed in this common flux

path. It is also feasible to place a “shield” band of conductive material in this chamber. This shield technique is similar to a “belly-band” copper screen often added around the outside of a conventional inductor or transformer to reduce radiated magnetic emissions.

The PIM method of Fig. 7 has the advantage of keeping the overall height of the core structure low. However, it is obvious that the surface area of the PIM will be increased

over the “stacked” arrangement of Fig. 3, requiring more area for mounting. Also, to access the inductive winding, holes must be placed in the bottom part of the inner core chamber. It is also conceptually possible to add a third outer chamber and associated core walls to the outside part of this core system for another set of inductive windings. However, since the winding lengths will be much longer than those of the innermost chambers, the copper losses will be higher than those in the three-chamber “stacked” design approach illustrated in Fig. 5.

Many power converter systems require multiple inputs or outputs that, in turn, require additional inductances for filtering purposes. These inductances can be placed in a PIM

in “coupled-inductor arrangements ” [1][3] in the appropriate chambers. For example, in the PIM design shown in Fig. 5, leakage inductance values between windings mounted in the

upper or the lower chambers can be well controlled by the addition of thin disks of core material [11], often termed “magnetic shunts”, or “reluctance disks” when windings are

implemented in PCB formats. Such disks can be used to provide magnetic control and reduction of AC current levels in selected inductor windings [1][2][4]. Examples of reluctance disk forms are shown in Fig. 10. Suitable disk materials include inexpensive varieties of cold-rolled steel and low-permeability soft ferrite. Disks of non-magnetic materials can also be used in those instances where desired leakage inductance values needed are small.

V. PIM MODELING METHODS

To facilitate a better understanding of the magnetic operations of the PIM designs shown earlier in Figs. 5 and 7, equivalent circuit models can be developed, using the reluctance-to-inductance modeling methods described in Chapter 12 of [1]. These models can then be used to study the dynamics and magnetic interactions between the transformer and inductive sections of a PIM. For example, using the flux paths and directions defined

earlier in Fig. 6 for the three-chamber PIM structure of Fig. 5, a first-order reluctance model of the magnetic system is formed, along with MMF sources. This model is illustrated

in Fig. 11. Note that the symmetry of the basic model permits it to be simplified as indicated in this sketch.

With a base reluctance/MMF model established, it can be converted into one involving inductances and excitation sources. This new model is shown in simplified form in Fig.

12. In this model, all inductance values are referred to winding NP of the PIM system in Fig. 5.Values for the inductances indicated in Fig. 12 can be estimated, using the first-order reluctance and inductance relationships defined in Table I. Examination of the resultant circuit model in Fig. 12 shows that that the two inductances (Lit and Lib) formed by

the two core pieces separating the two inductive chambers from the transformer chamber will be much larger in value than those associated with the upper and lower core pieces

where air gaps are present (Lct and Lcb). For this reason, very little of the flux developed by the transformer actions within the center chamber will appear in the core areas ssociated

with the inductor chambers. This confirms that transformer and inductive operations in this PIM will indeed be largely independent, with very little interaction between them.

Finally, as an example of the use of this circuit model in analyzing its use in conjunction with a converter network, TABLE I. Approximate relationships between the reluctances of Fig. 11

and the inductances shown in Fig. 12. airgap top airgap bottom mat center T B M cp top cp bottom mat cp center mat top mat middle sides mat mat top mat mat middle sides mat bottom Fig. 13. The forward converter circuit of Fig. 5 with the PIM equivalent model from Fig. 12. Fig. 13 is a circuit diagram of the forward converter system of Fig. 5, redrawn to include the PIM model of Fig. 12.

VI. PIM PROTOTYPE TESTS

To verify the “stacked” PIM approach illustrated in Fig. 5, a 200 kHz, 20-40VDC in, 5V-10A out, PIM forward converter system was designed, built and tested for performance, as a part of a recent NASA SBIR Phase II proposal effort. In this case, a three-chambered PIM was

constructed by using four separate cylindrical pieces of soft ferrite of the MN8CX variety made by Ceramic Magnetics. Overall height of the PIM structure was 16.8 mm (0.661 in)

and its diameter was 35.2 mm (1.386 in). Center post area in all chambers was set by design to 53.5 mm2 (0.076 in2 ), with the air gap lengths in the upper and lower chamber center posts cut to 254 mm (0.01 in). The primary and input inductor windings used 3 paralleled 8-turn double-sided PCBs, while the secondary and output inductor windings

used 3 paralleled double-sided 5-turn PCBs. Four-ounce copper patterns were used for all PIM PCB windings.

Measured inductance of the primary winding, the input filter inductor and the output filter inductor was 250 mH, 19.2 mH and 7.5 mH, respectively, very close to design projections. The measured efficiency of the power stage under maximum loading conditions was 87%, with total PIM core and winding power losses measured at nominally 1.2 watts. The measured temperature rise above ambient of the PIM was 30°C (no heatsink or forced-air cooling). As predicted by design, no discernible magnetic interactions were observed with regard to the transformer and inductive functions within the PIM during the testing of the converter. Core volume and weight savings over a conventional converter design having two individual planar inductors and one planar transformer were calculated to be 29.5%.

Similar verification testing of the “side-by-side” PIM system shown earlier in Figs. 8 and 9 have been reported by research engineers in Japan [9][10] with equal success. In one experiment, an off-line 100VAC-to-24VDC, 125W, 350 kHz forward converter system was built and tested. The PIM was constructed using a high-frequency low-loss ferrite of the 2500B2 variety made by TOKIN (Sendai, Japan). The outside diameter of the PIM was 53 mm (2.09 in), and its height was 8 mm (0.315 in). Total center post gap length was set at nominally 300 mm (0.012 in) to yield an output filter inductance of 16 mH. A 5-turn primary winding and a 3-turn secondary winding were used in the outer chamber, with an inner 6-turn inductor winding. Two-ounce copper patterns, nominally 70 mm (0.0028 in) thick, were used for all multilayer windings to minimize high-frequency copper losses.

The efficiency of the PIM of this converter system was measured to be on the order of 98% at an output power level of 125 watts. Noise reduction tests were also conducted, showing 10 to 20 dB reductions in 100-300 MHz radiated noise over that of a comparable converter design with separate “open-frame” inductor and transformer elements.

VII. CONCLUSIONS

The stacked “top-to-bottom” and “side-by-side” multichambered PIM constructions presented herein are new, volumetrically efficient IM techniques for blending the many

inductors and transformer functions of any dynamic power processing system without compromising electrical performance needs. The constructions can also include simple planar “disks” of magnetic material to control leakage inductances in selected areas of the structures. The form factors for the “top-to-bottom” construction variations can be either “open” or “closed”. In the former case, these PIMs can use standard circular core halves (e.g. pot, RM, PQ, DS shapes), or multiple E-I combinations of off-the-shelf lowprofile

rectangular cores. Research is continuing on these new PIM designs, including investigations associated with direct depositing of windings on selected parts of the core

structures to further reduce cost and assembly time.

ACKNOWLEDGMENTS

The author would like to acknowledge the electronic assembly funding support provided by the U.S. National Aeronautics & Space Administration (NASA) in the early phase of development [12] of the “stacked” PIM concepts described in this paper. A U.S. Patent [7] was issued to the author’s company in 1998 relative to this PIM method and other related enhancements.

Driving Prototype SMT Assembly with Power PCB

5. Details of Part Feeding Attributes

While the software required to compile a BOM into a set of tray definitions becomes complex the attribute set is fairly manageable. For each in house part number 4 lines of text have been setup in a Parts & Vendors database. These lines define:

‧ PCB Decal and Package Type

‧ Assembly ID and Placement Offsets

‧ Part Feeding Information

‧ Part Storage and Bin Location Data

While PowerPCB attributes can contain this data Index Design favor the uses of database techniques as this simplifies the writing of processing software.

The first line is used to define the Power PCB Assembly decals associated with Part Number. If a single string exists (as in the above example) then the decal for PCB design and for placement verification have the same name.

Line 2 (Asm_ID RXY) identifies the assembly machine ID for this component along with the Rotation, X and Y offsets. These offsets are used to translate from PCB design files to assembly machine formats. MyData machines use Unix based file systems and the legal

character set is small. A lookup table is constructed from the Parts & Vendors data as to allow third parties to setup and maintain their own translation tables.

Line 3 (Part Feed) identifies this part as being feed in a tray using a 0603 hole size that is 050 mils deep. The part is located in the tray at 0 degrees. Code in the BOM to tray “Compiler” uses this line to place the part into an inventory of predefined trays. Additional code takes the hole size name (0603 in this case) and drives a laser cutter that creates cardboard component trays. Cardboard trays are very useful as they are very space

efficient and they make it easy to visually verify that all parts for a job exist and are ready for placement. The hole depth field allows machined tray holes to be adjusted to match component height. Having small parts in controlled depth holes simplifies the packaging

of loaded trays and simplifies transport.

Line 4 drives component bin marking and locating functions. When gathering material for prototype assembly a significant amount of time is spent locating parts. Index Designs has set up a system where standard resistor and capacitors are stored in a loose form. It is much faster to reach for a small marked “Pill Box” and extract two or three loose parts than it is to locate a reel and extract 2 parts from tape.

Locating parts from inventory is a significant task. While reels are the most common form of individual part storage reels are difficult to store in an easy to locate and access manner. Index designs strips down a portion of its common reel components into pill boxes and sorts these into carriers based on size and type. A single carrier might carry 0603 capacitors while another might carry diodes.

The goal is to reduce the time it takes to load components for a job. Tray loading from loose parts in pill boxes averages about 350 parts per hour or about $0.09 per part. Loading of tape strips results in a loading rate of 2000 parts per hour. A medium sized board might contain 250 parts, which results in a worstcase setup of $18.00 per board. The threshold for moving from loose to tape strips is about 10 or 15 parts.

The BOM Compiler arranges the parts into trays such that loading errors are minimized. Experience shows that most part errors are generated as components are selected from storage. Bar Codes have been added to storage container bottoms to allow software verification of the selected component. In addition to bar codes laser cut trays are marked with component identifiers. While the loading of trays is tedious it is actually much faster than loading bare boards and the loading of reels is also a very tedious process. The goal is to minimize setup time. Whichever scheme prepares the assembly machine fastest is preferred.

Small parts typically load at 400 pieces per hour. Since all parts of one type are loaded at one time in a single row stuffing errors are practically eliminated. The small shallow holes in the tray surface allow parts to “Click In Place” which greatly speeds loading.

6. Schematic to PCB Tools

Once an external database is used to manage part placement it is relatively simple to expand this scheme to include Part Number to PCB Decal assignment. Index Designs provides PCB design services for a number of customers who use a variety of schematic

capture tools. In these schematics it is very common to find passive components with VALUES defined and some parts with incomplete manufacturer part numbers. Prior to PCB design the schematic items must be linked to PCB package styles as defined in the Index Designs library. Once all schematic items are mapped to physical packages the PowerPCB netlist is modified with the package assignment from the database. The resulting netlist is simply imported into PowerPCB.

The advantage to this scheme is that the schematic need not be changed to modify decal assignments and additional components (such as mounting holes) are easily added. Part value and reference designators from the original schematic are retained and BOM

compare function can detect changes in values, reference designator, pick and place setup, part location, rotation or side. These checks are very useful in detecting changes between revs. In many organizations a schematic BOM drives the generation of various supporting documents. The ability to detect and report a BOM change simplifies the task of

updating these documents and improves their accuracy.

“attributes” into schematic libraries is eliminated. Only a single resistor symbol is required in the schematic symbol library. Design engineers can concentrate on schematic Connectivity” with “BOM Annotation” saved as a final process.

The use of a reference schematic from vendors or schematics from consultants is simplified since write access to the schematic is not required. Consultants often have their own schematic tools and libraries andmost library data servers are not accessible through

company firewalls. Given the wide electronic assembly acceptance of the PowerPCB netlist format it is relatively simple to accept input from most any schematic capture program and map the designer part requirements to existing inventory parts.

RoHS Compliant PCB Assembly

The advent of the RoHS legislation which is due to come into effect from 1st July 2006 has caused a lot of electronics manufacturing companies and electronic component suppliers to review their product and service offerings. One such company is Ultra Electronics CEMS, the Dorset based electronic manufacturing services provider. Ultra CEMS manufactures products on behalf of their clients and has customers who are currently exempt from the current legislation as well as clients who are directly affected by the RoHS legislation.

John Dean, Sales Manager at Ultra CEMS states, “We are working with all of our clients at present to aid the transition to RoHS compliant components and products. We are advising even those companies who are currently exempt from the new legislation to review their component engineering strategy now as we believe PCB Assembly these companies will be affected sooner rather than later as component manufacturers gradually transition their whole product range to RoHS compliant product in order to reduce their costs.

It is our belief that certain packages will shortly only be available in a RoHS compliant form so it would be better to manage the change now rather have if enforced later. Even if component manufacturers continue to support non-RoHS compliant parts for the Defence, Aerospace sectors etc it is highly likely that the unit prices of these components will increase to reflect the lower volumes required. This is clearly something that will need to be considered in product costing/design reviews.

We are already producing a number of RoHS compliant PCB assemblies for clients and in some instances have been carrying out lead free PCB assembly since July 2004."

In PCB Assemblies it is not uncommon to have in excess of 100 different components per product to review. If we assume each client has a portfolio of over 10 uniquely different products then we can be talking about in excess of 1000 part numbers which have to be reviewed. This can be a daunting task and should therefore be undertaken sooner rather than later. The process involves offering component engineering support to clients and literally going through all of their parts lists making recommendations and finding direct RoHS compliant alternatives as well as advising on topics such as backward compatibility.

If you are not already electronic assembly considering the RoHS legislation and how it will affect your business then its time to start now before the new legislation comes into effect.

Prototyping Adapter Simplifies Device Test

As personal wireless connectivity is becoming more widespread and more complex, the ability to provide service on the many levels available to wireless users using a variety of devices is also rapidly becoming much more complex. To accommodate these challenges and to face a future where there are no barriers to access using a handheld device, engineers are investigating what measures are needed to create a "universal communicator," a device that is capable of communicating regardless of the connection options available to the user.

There are several options for personal wireless communication currently available through service providers. The majority of users connect via cellular connections: either using the GSM family of networks (GSM, GPRS, EDGE, UMTS), or the CDMA family of cellular networks (CDMA, CDMA 2000, 1xRTT, EV-DO, EV-DV). However, with the advent of wireless standards for WLAN and WMAN, deployment of these networks is steadily increasing in enterprises, public "hotspots" and even within homes. Although widespread deployment is still a few years away, these networking options are open to users now.

Additionally, various Wireless Personal Area Network (WPAN) technologies are emerging as well. Bluetooth is well on its way to becoming the most widely deployed WPAN technology in handsets and other devices -- with projections of nearly 300 million Bluetooth-enabled devices in the marketplace in 2007 (WLAN and Bluetooth PCB Assembly Update: Beyond the Hype, Forrester Research, June 16, 2003). Looking a few years down the road, Ultra Wideband (UWB) holds great promise as the next major technology for high-bandwidth wireless personal area connectivity.

Finally, a number of other wireless technologies are in the midst of being tested and/or deployed. For example, GPS is slated to ship in over 10 million phones this year, and several major device manufacturers are already shipping products with TV and/or radio receivers. Several operators and OEMs are also experimenting with including digital video broadcast (DVB) receivers in handsets, in some cases with GPRS used as a back channel to enable interactive data delivery (otherwise known as "datacasting").

Designs for future handheld devices will require that engineers consider each of these technologies and the challenges that each of these technologies pose in creating a device that can communicate regardless of the networking technology available.

A New Class of Device

Meeting both the opportunities and challenges of a heterogeneously-networked environment will require that handheld devices evolve considerably -- from the limited (often fixed-function and fixed-network) devices that predominate today, to powerful, flexible devices that can intelligently interact with multiple, heterogeneous networks and services.

This evolutionary process will result in the development of a new class of handheld device, dubbed a "universal communicator." A universal communicator-class device is a flexible, powerful personal communication device that provides users with transparent access to any available network, at any time, including the ability to seamlessly roam across those networks. Such a device must also provide support for key usage models that are made possible by a mixed-network environment. These usage models include:

Infofueling (smart data transfers using best available/most appropriate network)

Simultaneous voice and data sessions

Rich media that scales across networks (for example, video quality increases in a higher-bandwidth environment)

Cross-network voice, including support for seamless handoff

Location-based services

The focus of Intel's prototype device is by its capabilities rather than by a specific form factor. Users will continue to demand many different mobile form factors suited to their specific needs and lifestyles. For this reason, Intel efforts with the "Universal-communicator" device prototype are directed at delivering the overall platform capabilities needed to enable such devices.

Technology Challenges

Enabling such ubiquitously-connected devices poses numerous difficult technology challenges. These include:

Multiple Radio Integration and Coordination: Building the handset (or other device) begins with the challenge of integrating multiple radios.

Intelligent Networking -- Seamless Roaming and Handoff: Users will expect to roam within and between networks like they do with their cell phone.

Power Management: As handsets and other devices evolve to run more rich applications, power management will become an even greater challenge.

Support for Cross Network Identity and Authentication: Providing a trusted, efficient and usage-model appropriate means of establishing identity is one of the key issues in cross-network connectivity.

Support for Rich Media Types: The addition of a high-bandwidth broadband wireless connection, such as a WLAN or some of the forthcoming UMTS or EVDV/O cellular networks, will open up new opportunities for the delivery of rich media to handheld devices.

Flexible, Powerful Computing Platform: The foundation of a universal communicator-class device must be a flexible, powerful, general-purpose processing platform.

Overall Device Usability: The final challenge inherent in building a mixed-network device is usability.

To address these challenges, Intel engineers are developing a suite of key client technologies that can enable transparent, ubiquitous connectivity, as well as an architecture that pulls that set of technologies together into a coherent whole. Intel has dubbed that suite of technologies and the associated architectural framework, Adaptive Communication Technologies (ACT). As Intel develops these building blocks, Intel will diffuse this technology either via Intel silicon and platforms, or through cooperative efforts with other industry leaders and/or application developers.

The Prototype Concept

As a starting point for ACT development efforts, Intel has developed a first-generation universal communicator handset prototype. This prototype not only demonstrates the ability to successfully integrate multiple network access capabilities (in this case WWAN+WLAN) in a handset, but also demonstrates several key technologies and design principles that Intel believes are applicable to a larger class of universal communicator-class devices.

The universal communicator prototype demonstrates key usage models for mixed-network handheld clients, including:

Simultaneous data and voice sessions

Infofueling -- smart data transfers using best available network

Rich media that scales across network connections

Voice (cellular and VOIP) across multiple networks

A Feature-Rich Handheld Device

The prototype incorporates many advanced features and technologies that enable important usage models

Intel PCA processor -- Based on Intel XScale technology, this processor provides a powerful, general-purpose platform upon which to build wireless applications and makes possible many advanced features, including Voice-Over-IP, high-quality audio and video, and enhanced 3D gaming.

Integrated 802.11b and GSM/GPRS radios, with component decoupling -- The UC handset prototype uses an embedded 802.11b module for onboard WLAN capability. The module implementation is a complete solution on a PCB substrate, which comes with fully shielded and attaches to the board via BGA technology. It supports the PCMCIA interface for system control and requires the addition of only address and data bus buffering components to isolate from the main system bus as well minimal control circuitry and a discrete antenna. The implementation includes power supply isolation through an LDO regulator and uses an internal chip antenna.

The GSM/GPRS solution is implemented using an Intel-developed GSM/GPRS module. This module supplies the complete baseband/RF solution and requires the addition of a discrete, external antenna. System connectivity/control is achieved via a high-speed serial interface, and our design implements a separate audio codec subsystem for speaker/microphone and ringer components. The GEM module is a complete solution on a PCB substrate which is fully shielded.

Mobility Management Driver Stack (MMDS) -- Mobility management is the ability for a client device's applications and operating system to discover the in-proximity wireless network environment and then interact with the networks within that environment in complex ways.

The MMDS stack in the current prototype supports a subset of three general categories of functionality: heterogeneous wireless network detection; quality of service characterization; and ultimately support for seamless hand-offs between networks. By taking a cross-network perspective (IP or otherwise) to these problems the MMDS approach is different, albeit complementary, to single-protocol approaches such as Mobile IP. The remainder of the section describes in more detail the work Intel has done in the prototype relative to these functional categories.

Voice Call Unification Architecture (VCUA) -- In the special case of a voice call, support for uninterrupted call audio is required in addition to network hand-off to deliver a seamless user experience. The prototype VCUA in the prototype abstracts device audio resources so that the audio session continues even if the underlying audio hardware changes.

Taken together, the VCUA and the MMDS enable seamless call handoff. In the prototype, a specially-modified version of the Telesym SymPhone client software utilizes these capabilities to deliver a relatively seamless call handoff between networks.

Antenna layout, shielding, and optimal spatial positioning reduce analog radio interference -- The prototypes uses the Galtronics "Wind Back" antenna to provide optimal GSM reception which is shielded to avoid analog radio interference.

A chip antenna was used for the internal IEEE 802.11b subsystem and used similar implementation techniques as those used for the GSM antenna interface: plane voids, CPW, routing obstructs on all trace layers, etc.

Advanced media capabilities -- The handset prototype contains a high-performance, software H.264/AVC video decoder for playback of local and streaming content over a variety of network connections. The decoder is compliant with the Baseline Profile, and is optimized for Intel Wireless MMX technology.

Usability -- The prototype contains a number of technologies designed to increase usability for wireless applications such as a Kodak NuVue OLED (organic light-emitting diodes) display which requires no backlights and provides clearer images and crisper video.

The UC handset prototype also features a Fastap keypad. The Fastap keypad hardware and software provides direct-entry alphanumeric input, allowing mobile phone users to create text and multimedia messages quickly and intuitively.

SD card slot -- Support for SD cards provides the opportunity for additional storage -- critical for many data-intensive wireless applications.

Summary

Building a handheld device that can be considered a "universal communicator" will require that engineering teams consider the many challenges that will face its development. The result of that evolutionary process will be a new class of devices that will use multiple networks to transparently connect users with information and services.

Intel is developing a core set of technology building blocks -- called Adaptive Communication Technologies -- that will enable seamless, transparent connectivity and advance efforts at universal connectivity and communication. Concept platforms like the Universal Communicator handset prototype provide a research platform for the development, integration, and validation of these technologies. In addition, Intel is working electronic assembly with the high-tech industry to develop and distribute the key technologies and research required to make universal, transparent connectivity a reality.

Prototyping techniques help verify analog-circuit performance

Figure 2 shows another prototype in which a single-sided copper-clad Vectorboard has

predrilled holes on 0.1-in. centers. Power buses are at the top and bottom of the board.

The power pins of each IC have their own decoupling capacitors. Because of the loss of

copper area due to the predrilled holes, this technique does not provide as low a ground impedance as a completely covered, copper-clad board.

A variation of this technique is to mount the ICs and other components on the non-copper-clad side of the board. The holes serve as vias, and you do the point-to-point wiring on the copper-clad side of the board. To prevent shorts, you must drill out the copper surrounding each hole used for a via. This approach requires that all IC pins be on 0.1-in. centers. You can use low-profile sockets for low-frequency circuits, and the socket pins allow for easy point-to-point wiring.

One commercial breadboarding system has most of the advantages of robust ground, screening, ease of circuit alteration, low capacitance, low inductance, and several additional advantages. The system is rigid, has components that are PCB Assembly close to the ground plane, and lets you easily calculate node capacitances and line impedances. The product is available as "Mini-Mount" in Europe from Wainwright Instruments

GmbH (Andechs-Frieding, Germany) and as "Solder-Mount" in the United States (where the trademark "Mini-Mount" is the property of another company) from Wainwright Instruments Inc (San Diego, CA).

Solder-Mount comprises small pieces of pc board with etched patterns on one side and

contact adhesive on the other (Figure 3a). The pc-board pieces stick to the ground plane, and you can solder components to the pieces. The board pieces are available in a variety of patterns, including ready-made pads for eight-pin SOICs to 64-pin dual-in-line types; strips with solder pads at intervals ranging from 0.040 to 0.25 in., including strips with 0.1-in. pad spacing, which you can use to mount dual-in-line devices; strips with 50, 60, 75, or 100_ conductors to form microstrip transmission lines when you mount them on the ground plane; and a variety of pads for mounting various other components.

The conductor-strip feature of Solder-Mount at VHF is convenient. You can use these strips for 3 von 8 9/25/00 4:09 PM EDN -- 02.15.96 Prototyping techniques help verify analog-circuit performance http://www.ednmag.com/reg/1996/021596/04df3.htm

transmission lines, impedance matching, or power buses. Glass-fiber/epoxy pc board is somewhat lossy at VHF and UHF, but the losses are probably tolerable if microstrip runs are short. Self-adhesive, tinned copper strips and rectangles (LO-PADS) are also available as tie-points for connections. These strips have a relatively high capacitance to ground and, therefore, serve as low-inductance decoupling capacitors. The strips come in sheet form, and you can cut them with a knife or scissors.

The main advantage of Solder-Mount construction over bird's nest or dead-bug construction is that the circuit resulting from using Solder-Mount is stiffer and, if an application requires, smaller. The latest Solder-Mounts for surface-mount devices let you construct breadboards scarcely larger than the final pc board. It is generally more convenient if the prototype is somewhat larger than the final breadboard, however. Solder-Mount is durable enough for low-quantity production. A 2.5-GHz PLL prototype built with Solder-Mount (Figure 3b) is a high-speed circuit, but the technique is equally suitable for the construction of high-resolution, low-frequency analog circuitry.

Both the dead-bug and Solder-Mount techniques become tedious for complex analog or mixed-signal circuits. Formal layout techniques often produce better prototypes of large circuits. One approach to prototyping more complex analog circuits is to lay out a double-sided board using CAD. PC-based layout packages offer easy layout and schematic capture to verify connections. Such packages are available from PADS Software (Marlborough, MA) and Accel Technologies (San Diego, CA). Although

most layout software offers some autorouting capability, this feature is best left to digital designs. After you place the components in position, manually route the interconnections following layout guidelines (Reference 3). After you complete the layout, the software verifies the connections against the schematic diagram's netlist.

Many design engineers find that they can use CAD techniques to lay out simple boards or work closely with a layout person who has experience in analog-circuit boards. The result is a pattern-generation tape or Gerber file, which you normally would send to a pc-board-manufacturing facility, which makes the final board. Rather than use a pc-board manufacturer, however, you could use automatic drilling and milling machines that directly accept the pattern-generation tape. These prototype-board cutters are

available from LPKF CAD/CAM Systems Inc (Beaverton, OR) and T-Tech Inc (Atlanta). These systems directly produce single- and electronic assembly double-sided circuit boards by drilling all holes and then using a milling technique to remove copper, create insulation paths, and create the finished board.

Get a Deep Insight into the Advanced Printed Circuit Board

Reportlinker.com announces that a new market research report related to the Component industry is available in its catalogue.

Advanced printed circuit board or PCB Assembly, refers to the fields requiring a high entry threshold. IC substrate has a closer relationship with semiconductor packaging, so it is beyond the research scope of the report.

In 2007, China's mobile phone output exceeded 600 million units. At present, 90 percent of mobile phones adopt HDI board. Based on the estimation that one square meter of HDI board fits the production of around 180 units of mobile phones, we get the results that the market demand of China's mobile phones for HDI board is 3 million square meters. In addition, from the perspective of production capacity of China's key HDI manufacturers, China's HDI production capacity still can not meet the rapid growth in market demand, although some manufacturers have expanded their production capacity. The companies in Mainland China that are able to mass produce HDI board include Multek Corp., Compeq Manufacturing Co., United Power, AT&S, Ibiden, Shanghai Meadville, Shantou Goworld, Huafeng Weixian, Meiko, and Shanghai Unitech Electronics Co., Ltd.

Multek is a large PCB works affiliated to Flextronics, and United Power is the subsidiary of Unimicron, the world's largest handset PCB producer, which supplies PCB for Nokia and Motorola via Foxconn. Compeq Manufacturing (Huizhou), with Motorola as its key client, is the unit of Compeq, Taiwan's mobile phone PCB producer. AT&S is the subsidiary of Austria AT&S in Mainland China. Ibiden with Nokia as its sole client is based in Beijing. Shanghai Meadville is affiliated to Hong Kong Meadville Group, and Huafeng Weixian is a unit of Daisho Microline Holdings Ltd. Meiko is of the ability of mass production, but its main business is focused on flat-panel TV and automobile. Shanghai Unitech is the subsidiary of Taiwan Unitech. Among these companies, only Shantou Goworld belongs to Mainland China.

Due to the successive price cut in the promotion of laptop, HDI laptop market is limited mainly to several types with screen size below 13-inch in consideration of cost, although Intel gives much support. HDI laptop market currently amounts to 10 percent of laptop shipment and HDI design won't be introduced completely to the laptop market due to cost. HannStar and Gold Circuit Electronics Ltd. jointly dominate the global laptop PCB market, taking up 75 percent of the market, and the rest market is shared by Unimicron, Compeq and Unitech. Market entry threshold is very high for a new entrant.

Entry barrier for memory board is not low as well. Gross profit margin of memory PCB board is very low, at most about 10%, and profit will be a single digit, given deduction of related operating expenses. Only large scale production of memory board can be profitable, especially considering equipment depreciation. The global leading memory PCB board manufacturers are SIMMTECH in South Korea and Tripod, both of which occupy more than 80% of the global market.

At present, Tripod is still the largest photovoltaic panel producer in Taiwan. WUS Printed Circuit Co. believes that TFT-LCD industry has entered a period of maturity, and it is impossible to again achieve a rapid growth in the electronic assembly industry. Furthermore, TFT-LCD market fluctuates much, so WUS Printed Circuit decided to exit photovoltaic panel field, and to focus on PCB for mobile phones and laptops. After the exit of WUS Printed Circuit, Taiwan PCB TechVest Co. entered the market aggressively.

As for auto electronics PCB market, the entry threshold is even higher. The well-known manufacturers in the market include Viasystems Group, CMK, Meiko, Jinghua in Mainland China and Unitech in Taiwan. The market has maintained its layout for many years.

RF Module Design: Requirements and Issues

At the hub of a top-down design flow for an RF-system-design-to-product implementation is the RF module design for RF integrated circuits (RFICs), boards and a final RF system prototype. Both RF module design and prototype development are receiving lots of industry and electronic design automation (EDA) attention today due to three factors: rapid growth in module business coupled with growth in system and module complexity; multiple RFIC manufacturing passes costing approximately $1 million per pass; and a production bottleneck at the system/module prototype test.

Multiple RFIC manufacturing passes often result from the lack of design tool interaction between design domains (IC to module), and an inability to accurately model RF load effects of the RFIC in the target RF module. Increasing RF module and system complexity have spawned the need for more accurate models of various module implementations so system engineers can make proper system performance and cost trade-off decisions. A lack of EDA tool integration and/or standard data-interfaces for the various design disciplines — such as the RF system, printed circuit boards (PCBs), IC packages and IC designs, and prototype testing — have contributed to the difficulty of achieving more accurate models.

This article will highlight these issues and discuss PCB Assembly appropriate solutions for related RF module design examples. It will explore:

RF module performance in an RF system model;

Two types of RF module technologies;

An RF module design example of accuracy problems — 802.11 XCVR multichip module;

Design tool flows and interfaces;

Design concurrency and regression; and

What's feasible today and what's possible for tomorrow.

RF module performance in an RF system model

Usually more than one level of abstract representation exists for the RF module and functional blocks within the RF system, facilitating varying degrees of simulation/evaluation accuracy. Three levels of design abstraction representation are defined below.

‧ Algorithmic architecture levels (Level I), derived from SystemC, C/C++, Microsoft's Excel spread sheets, Cadence's signal processing worksystem (SPW) or Ptolemy libraries. An entire suite of stimulus standards, channel models, air interfaces and measurement blocks contribute to the development of the full RF system test bench for bit error rate (BER) and error vector magnitude (EVM) simulations.

2. Level II of model representation consists of a more accurate and comprehensive behavioral model (VHDL, VHDL-AMS, Verilog, Verilog-A/AMS or C/C++) of RFIC functionality with board parasitic effects or electromagnetic (EM) models and discrete device/component models (S-Parameters). The Level II model is useful for refining performance analysis accuracy to a second order of parameter analysis and simulation accuracy within the RF system. A Level II model also, in most cases, is a representative model for intellectual property (IP) reuse of various functions (such as low noise amplifier, mixer, voltage controlled oscillator, in-phase and quadrature demodulation).

3. Level III of RF module modeling is at the device/component level or circuit schematic. Only a true mixed-signal simulation EDA tool such as the Cadence Design Systems Inc.'s AMS Designer or Mentor Graphics Corp.'s ADVanced MS can provide reasonable and efficient simulation/analysis of design representations of blocks at this level. Most often, due to design complexity, only mixed-level simulation (one block at behavioral level, with other blocks at circuit level) can be facilitated within a reasonable amount of time, such as a few days, versus several days to weeks.

Another area of modeling, known as data characterization models or model extraction technology is quickly becoming a crucial part of the total solution. It offers the best accuracy and simulation throughput time for final system, module and block regression testing. Several companies, including Cadence, Agilent Technologies Inc. and Xpedion Design Systems Inc. are developing “data characterization modeling” methods and technologies. All of these modeling methods address the need for design regression validation. In many cases, the value of these models for RF systems and RF module design is greatly enhanced when they are an “extraction” of real data/performance or final circuit simulations of RF module/RFIC functions in the test lab. “Model extraction” technology is also a key enabler for fully facilitating design IP reuse.

Therefore, the entire issue of RF systems/RF module simulation/evaluation accuracy can be addressed with two critical pieces of technology:

Behavioral models of a common language (C/C++, VHDL, VHDL-AMS, Verilog, Verilog-A/AMS), and

Data characterization models of standard formats (S-Parameters, table-based behavioral models, extraction models).

If both technologies were readily available today — and supported by the major EDA tool suppliers and common to the system, module, IC, and package design domains — actual usage would occur at a reasonable adoption rate if and only if:

Credible libraries of behavioral models for RF and analog functions existed requiring minimal customization; and

Data characterization and extraction modeling technologies had been validated for performance/accuracy and simulation throughput for a classical RF system top-down design flow.

Two RF module technologies

It's important to consider the types of physical media used for RF module assembly, due to the variations of RF passives library requirements, resident EM field solving technologies, and access to IC package parasitic modeling that may or may not exist for PCB and IC design tools.

Most Common RF module Configurations

RF Module physical assembly technologies include:

Various dielectric substrates depending on application (such as FR4, PTFE), high temperature cofired ceramic (HTCC) or low temperature co-fired ceramic (LTCC);

Multilayer wiring with plated through hole (PTH) and via layer connect technologies; and

Surface mount devices/components (SMTs), chip-on-board (COB), IC package on board, thin/thick film components.

An RF system and/or RFIC designer must be able to fully model and analyze the RF module within each respective design domain. Further, these designers must have access to S-Parameters for surface-mount components from discrete device component vendors, S-Parameters for EM effects of PCB parasitic effects, and mathematical expressions of discrete device behavior (such as RF nonlinearity for a varactor diode) using Matlab or C/C++ equations.

These models must be available or already linked into the system and IC design domains. This capability has enabled a complete, accurate RF module target-design that surrounds the RFIC.

What's missing from this type of RF module modeling is the ability to import and use other EM Field Solver tools and models, noise and cross-coupling analysis technologies from the PCB design domain, and other special discrete device and component models (equations and S-Parameters) not currently supported by the PCB design tool's library.

It's important to note that an IC package design and analysis tool is not part of the data-interchange capability of the RFDE tool, because this tool is part of the PCB design tool environment.

Advanced RF Module Configurations

The most distinguishing characteristic of advanced RF module configurations can be summed up in the terminology of imbedded passive devices (IPDs). This means that advanced RF module passive devices (such as resistors, capacitors, inductors, and micro-strip lines) are embedded within the silicon-on-substrate or sandwiched between layers of the combination of LTCC and metal (LTCC-M) compositions.

Why is this different than common RF modules, or why is it even an issue? IPDs are created and design-sized at the RF module and/or RFIC design stage. Therefore, RF component characterization and modeling must be done as a custom library development effort.

If advanced RF module an LTCC-M type, the IPDs are modeled and characterized within the PCB design domain in cooperation with the LTCC-M process foundry. The IPD library and its design components are available to the design engineer as part of the IC design tool kit. The same is true for the silicon-on-substrate advanced RF module. To establish a fully characterized IPD library that's ready to use for advanced RF module design, significant modeling and device characterization work must be planned.

Advanced RF module design lacks a complete RF module and RFIC modeling environment. For example, EM Field Solvers for silicon-on-substrate parasitic analysis and custom bond-wire modeling for COB of an LTCC-M are not necessarily available within the IC design tool environment.

Accuracy problems example

The following 802.11 XCVR multichip module design example shows the RFIC design accuracy risks when accurate models do not exist within the IC design domain of the RF module elements (such as passives, and substrate parasitics) interfacing to and from the RFIC.

The RF module consists of two RFICs, a diplexer/duplexer, an antenna, a module substrate, and surface-mount technology (SMT) components. Refer to figure 1.

Transmitter performance indices of the PA RFIC are evaluated because of the critical RFIC-to-RF module interface and load matching media. This example depicts differences in power-gain and noise accuracies for the transmitter simulation performance with distributed versus extracted (S-Parameter) load models for: SMTs, strip-lines, and board parasitics. Based on the simulation results shown in Table 1, power amplifier (PA) RFIC (and potentially the Tx/Rx RFIC) would require design modification if only distributed models were used for PCB components: ML1 to ML4, Cc, S1 to S3, and LP at the RFIC design domain.

Design tool flows and interfaces

RF top-down design flow and methodology forms the basic design process for accurate and efficient RF module design. The basic steps and data-interchange requirements are depicted in figure 2.

Flow step number 1: Top-level design at the RF system level is the beginning point of design and the end-point for regression validationand testing of the RF module within the RF system.

Table 2 describes the characteristics of design representation, the system design tool (basic) features, and data-interchange characteristics related to linking (bi-directional) of the RF module through the various design domains of RF module, RF module test, and RFIC.

The RF system model for the RF module (signal and stimulus, channel models and RF building blocks) becomes the “Golden Test Bench” (by linking to module and RFIC design domains) for the rest of the design flow.

Because most system design tools utilize synchronous data flow simulation architecture, the full set of S-Parameters for any discrete devices or components on the PCB cannot to be utilized at the RF system test model. However, in the technology development of data characterization models (in particular, low-pass equivalent models), modeling of S-Parameter effects during data characterization is being evaluated to better represent PCB environment impedance effects at the RF system level.

Flow step number 2: Re-validate system performance criteria (such as EVM) at the RF module/RFIC design domain. At this stage the RF module has been evaluated to Level I design modeling accuracy (architectural or algorithmic). The RF module model and input stimulus (via the Golden Test Bench represented in C/C++) are linked to the RF module/RFIC design domain. The RF module Golden Test Bench is re-evaluated with the module and IC design domain simulators (refer to table 2). A combination of time and/or frequency domain simulators are used (such as harmonic balance, envelope analysis or periodic steady state) to provide signal power and noise analysis capability.

This simulation process is one of “evaluate-by-observation” the performance of the RF module using the same (Level I) models, but using a different simulation technology than that used for the RF system simulation. All design data models and model parameters used in this Level I simulation are common to the RF system simulation. Only the simulator is different.

Flow step number 3: Replace RF module with behavioral models and component and board models (Level II design). This is the first stage of design refinement and structure definition beyond Level I representation. It is the first point of design accuracy improvement enabling design exploration and trade-off analysis. In addition, because the Golden Test Bench is being used to validate RF module performance, this is the first time within the flow that the RF module design is regression tested. Level II design simulation performance is compared directly (over-laid) to Level I performance.

Flow step number 4: Replace RF module with circuit schematics and keep accurate component/board models in place.

Flow step number 5: Replace RF module with data characterization models. Accurate simulation results from flow step number 4 are modeled in various forms (low-pass equivalent, extraction models depending on evaluation criteria), resulting in a very accurate RF module model (typically within five percent compared to Level III simulations) that is at least 100-times faster for simulation than Level III circuit simulations.

Finally, the RF Module of flow step number 5 is re-linked to the RF system and RF module design domains to close the final loop of bottom-up design regression validation.

Design concurrency and regression

The concept of “concurrent design” for IC silicon, IC package, PCB and prototype test development within the RF system design environment is a “must-do” requirement for meeting time-to-market demands and first-pass acceptable prototypes for today's RF systems.

The need for development of a concurrent design process is being driven by the demand for top-down design methodology for RF system, RF module and RFIC design, respectively. Further, the requirement exists to perform a final Golden Test Bench validation based on final design implementations, using a bottom-up regression design methodology at each design level: — RFIC-to-RF module, and later RF module-to-RF system.

Once system partitioning has been defined for boards and ICs, concurrent design, with iterative design refinement, should begin in conjunction with the top-down design flow shown in figure 2. Although design domains and tool database structures have been separate and independent entities in the past, market demands today require convergence and linkage.

The first steps for bringing together these design domains are the use of RF behavioral models functions using a common language, and provisions of various forms of data characterization model technologies (such as S-Parameters representing Field Solver analysis or extraction models), using measured or transistor-level simulated data from each design domain (such as IC, package, passive components, and board).

RF system and module design domains could be linked together effectively if the industry (design, test and EDA) would support and establish standards concerning the interaction of EDA design tools. Two important items to be standardized are a behavioral language (C/C++, VHDL, VHDL-AMS, Verilog, Verilog-A/AMS), and data characterization modeling formats (S-Parameter parameter or extracted into a C/C++ model).

Open Access (common database) is an important industry initiative that can further facilitate concurrent design for system, PCB and IC design domains.

What's feasible today and possible for tomorrow?

Design technologies available today include:

Behavioral models;

Extraction modeling techniques;

Data characterization models — sometimes referred to as table-based modeling; and

S-Parameters for discrete components and EM Field Solver parasitic effects.

All are available today within various EDA design tool environments, but not necessarily bi-directionally linked between design domains (such as PCB design to IC design).

Two other technologies that could be critical for the future for each design domain (System, IC, and PCB) are design-constrained (physical and electrical) floor planning, and combined analysis capability for noise and cross-coupling analysis and Field Solver integration.

The existence of design-constrained floor planning for ICs and separate/independent noise analysis technologies (substrate noise analysis, parasitic coupling analysis) is common knowledge. Some of these technologies also apply to PCB 21/2 D and full 3-D Field Solver technologies. What's lacking is the integration of these technologies for use at the “early design evaluation/ analysis” stage of design, including system, module and IC.

Industry demands of EDA suppliers should drive the need for this early design evaluation/analysis capability. To perform this first-order analysis, it is usually sufficient to utilize 21/2 D Field Solver and physical media input data; cross-section thickness, dielectric constants and conductivities for noise and parasitic coupling analyses.

Without the early design evaluation/analysis technologies, at best approximately 30 percent of field, noise and parasitic effects on the overall RF system and RF module design can be estimated.

Conclusion

EDA tools offer the capability to fully model, design and simulate an RF module, with some limitations and dedicated development of behavioral models. This existing capability can greatly reduce the very expensive risk of RFIC photo mask and silicon respins. However, system, board and IC design domains are not sufficiently interfaced to support a seamless, fully integrated top-down design environment. In addition, TTM requirements are forcing the need for RF system, module and IC designers to have readily available libraries for behavioral models, RF passives, and extraction models. When early design analysis technologies of design constrained floor planning and cross-coupling and substrate analysis are integrated within these design domains, RF module design accuracy will be much more comprehensive and precise.