RF Module Design: Requirements and Issues

At the hub of a top-down design flow for an RF-system-design-to-product implementation is the RF module design for RF integrated circuits (RFICs), boards and a final RF system prototype. Both RF module design and prototype development are receiving lots of industry and electronic design automation (EDA) attention today due to three factors: rapid growth in module business coupled with growth in system and module complexity; multiple RFIC manufacturing passes costing approximately $1 million per pass; and a production bottleneck at the system/module prototype test.

Multiple RFIC manufacturing passes often result from the lack of design tool interaction between design domains (IC to module), and an inability to accurately model RF load effects of the RFIC in the target RF module. Increasing RF module and system complexity have spawned the need for more accurate models of various module implementations so system engineers can make proper system performance and cost trade-off decisions. A lack of EDA tool integration and/or standard data-interfaces for the various design disciplines — such as the RF system, printed circuit boards (PCBs), IC packages and IC designs, and prototype testing — have contributed to the difficulty of achieving more accurate models.

This article will highlight these issues and discuss PCB Assembly appropriate solutions for related RF module design examples. It will explore:

RF module performance in an RF system model;

Two types of RF module technologies;

An RF module design example of accuracy problems — 802.11 XCVR multichip module;

Design tool flows and interfaces;

Design concurrency and regression; and

What's feasible today and what's possible for tomorrow.

RF module performance in an RF system model

Usually more than one level of abstract representation exists for the RF module and functional blocks within the RF system, facilitating varying degrees of simulation/evaluation accuracy. Three levels of design abstraction representation are defined below.

‧ Algorithmic architecture levels (Level I), derived from SystemC, C/C++, Microsoft's Excel spread sheets, Cadence's signal processing worksystem (SPW) or Ptolemy libraries. An entire suite of stimulus standards, channel models, air interfaces and measurement blocks contribute to the development of the full RF system test bench for bit error rate (BER) and error vector magnitude (EVM) simulations.

2. Level II of model representation consists of a more accurate and comprehensive behavioral model (VHDL, VHDL-AMS, Verilog, Verilog-A/AMS or C/C++) of RFIC functionality with board parasitic effects or electromagnetic (EM) models and discrete device/component models (S-Parameters). The Level II model is useful for refining performance analysis accuracy to a second order of parameter analysis and simulation accuracy within the RF system. A Level II model also, in most cases, is a representative model for intellectual property (IP) reuse of various functions (such as low noise amplifier, mixer, voltage controlled oscillator, in-phase and quadrature demodulation).

3. Level III of RF module modeling is at the device/component level or circuit schematic. Only a true mixed-signal simulation EDA tool such as the Cadence Design Systems Inc.'s AMS Designer or Mentor Graphics Corp.'s ADVanced MS can provide reasonable and efficient simulation/analysis of design representations of blocks at this level. Most often, due to design complexity, only mixed-level simulation (one block at behavioral level, with other blocks at circuit level) can be facilitated within a reasonable amount of time, such as a few days, versus several days to weeks.

Another area of modeling, known as data characterization models or model extraction technology is quickly becoming a crucial part of the total solution. It offers the best accuracy and simulation throughput time for final system, module and block regression testing. Several companies, including Cadence, Agilent Technologies Inc. and Xpedion Design Systems Inc. are developing “data characterization modeling” methods and technologies. All of these modeling methods address the need for design regression validation. In many cases, the value of these models for RF systems and RF module design is greatly enhanced when they are an “extraction” of real data/performance or final circuit simulations of RF module/RFIC functions in the test lab. “Model extraction” technology is also a key enabler for fully facilitating design IP reuse.

Therefore, the entire issue of RF systems/RF module simulation/evaluation accuracy can be addressed with two critical pieces of technology:

Behavioral models of a common language (C/C++, VHDL, VHDL-AMS, Verilog, Verilog-A/AMS), and

Data characterization models of standard formats (S-Parameters, table-based behavioral models, extraction models).

If both technologies were readily available today — and supported by the major EDA tool suppliers and common to the system, module, IC, and package design domains — actual usage would occur at a reasonable adoption rate if and only if:

Credible libraries of behavioral models for RF and analog functions existed requiring minimal customization; and

Data characterization and extraction modeling technologies had been validated for performance/accuracy and simulation throughput for a classical RF system top-down design flow.

Two RF module technologies

It's important to consider the types of physical media used for RF module assembly, due to the variations of RF passives library requirements, resident EM field solving technologies, and access to IC package parasitic modeling that may or may not exist for PCB and IC design tools.

Most Common RF module Configurations

RF Module physical assembly technologies include:

Various dielectric substrates depending on application (such as FR4, PTFE), high temperature cofired ceramic (HTCC) or low temperature co-fired ceramic (LTCC);

Multilayer wiring with plated through hole (PTH) and via layer connect technologies; and

Surface mount devices/components (SMTs), chip-on-board (COB), IC package on board, thin/thick film components.

An RF system and/or RFIC designer must be able to fully model and analyze the RF module within each respective design domain. Further, these designers must have access to S-Parameters for surface-mount components from discrete device component vendors, S-Parameters for EM effects of PCB parasitic effects, and mathematical expressions of discrete device behavior (such as RF nonlinearity for a varactor diode) using Matlab or C/C++ equations.

These models must be available or already linked into the system and IC design domains. This capability has enabled a complete, accurate RF module target-design that surrounds the RFIC.

What's missing from this type of RF module modeling is the ability to import and use other EM Field Solver tools and models, noise and cross-coupling analysis technologies from the PCB design domain, and other special discrete device and component models (equations and S-Parameters) not currently supported by the PCB design tool's library.

It's important to note that an IC package design and analysis tool is not part of the data-interchange capability of the RFDE tool, because this tool is part of the PCB design tool environment.

Advanced RF Module Configurations

The most distinguishing characteristic of advanced RF module configurations can be summed up in the terminology of imbedded passive devices (IPDs). This means that advanced RF module passive devices (such as resistors, capacitors, inductors, and micro-strip lines) are embedded within the silicon-on-substrate or sandwiched between layers of the combination of LTCC and metal (LTCC-M) compositions.

Why is this different than common RF modules, or why is it even an issue? IPDs are created and design-sized at the RF module and/or RFIC design stage. Therefore, RF component characterization and modeling must be done as a custom library development effort.

If advanced RF module an LTCC-M type, the IPDs are modeled and characterized within the PCB design domain in cooperation with the LTCC-M process foundry. The IPD library and its design components are available to the design engineer as part of the IC design tool kit. The same is true for the silicon-on-substrate advanced RF module. To establish a fully characterized IPD library that's ready to use for advanced RF module design, significant modeling and device characterization work must be planned.

Advanced RF module design lacks a complete RF module and RFIC modeling environment. For example, EM Field Solvers for silicon-on-substrate parasitic analysis and custom bond-wire modeling for COB of an LTCC-M are not necessarily available within the IC design tool environment.

Accuracy problems example

The following 802.11 XCVR multichip module design example shows the RFIC design accuracy risks when accurate models do not exist within the IC design domain of the RF module elements (such as passives, and substrate parasitics) interfacing to and from the RFIC.

The RF module consists of two RFICs, a diplexer/duplexer, an antenna, a module substrate, and surface-mount technology (SMT) components. Refer to figure 1.

Transmitter performance indices of the PA RFIC are evaluated because of the critical RFIC-to-RF module interface and load matching media. This example depicts differences in power-gain and noise accuracies for the transmitter simulation performance with distributed versus extracted (S-Parameter) load models for: SMTs, strip-lines, and board parasitics. Based on the simulation results shown in Table 1, power amplifier (PA) RFIC (and potentially the Tx/Rx RFIC) would require design modification if only distributed models were used for PCB components: ML1 to ML4, Cc, S1 to S3, and LP at the RFIC design domain.

Design tool flows and interfaces

RF top-down design flow and methodology forms the basic design process for accurate and efficient RF module design. The basic steps and data-interchange requirements are depicted in figure 2.

Flow step number 1: Top-level design at the RF system level is the beginning point of design and the end-point for regression validationand testing of the RF module within the RF system.

Table 2 describes the characteristics of design representation, the system design tool (basic) features, and data-interchange characteristics related to linking (bi-directional) of the RF module through the various design domains of RF module, RF module test, and RFIC.

The RF system model for the RF module (signal and stimulus, channel models and RF building blocks) becomes the “Golden Test Bench” (by linking to module and RFIC design domains) for the rest of the design flow.

Because most system design tools utilize synchronous data flow simulation architecture, the full set of S-Parameters for any discrete devices or components on the PCB cannot to be utilized at the RF system test model. However, in the technology development of data characterization models (in particular, low-pass equivalent models), modeling of S-Parameter effects during data characterization is being evaluated to better represent PCB environment impedance effects at the RF system level.

Flow step number 2: Re-validate system performance criteria (such as EVM) at the RF module/RFIC design domain. At this stage the RF module has been evaluated to Level I design modeling accuracy (architectural or algorithmic). The RF module model and input stimulus (via the Golden Test Bench represented in C/C++) are linked to the RF module/RFIC design domain. The RF module Golden Test Bench is re-evaluated with the module and IC design domain simulators (refer to table 2). A combination of time and/or frequency domain simulators are used (such as harmonic balance, envelope analysis or periodic steady state) to provide signal power and noise analysis capability.

This simulation process is one of “evaluate-by-observation” the performance of the RF module using the same (Level I) models, but using a different simulation technology than that used for the RF system simulation. All design data models and model parameters used in this Level I simulation are common to the RF system simulation. Only the simulator is different.

Flow step number 3: Replace RF module with behavioral models and component and board models (Level II design). This is the first stage of design refinement and structure definition beyond Level I representation. It is the first point of design accuracy improvement enabling design exploration and trade-off analysis. In addition, because the Golden Test Bench is being used to validate RF module performance, this is the first time within the flow that the RF module design is regression tested. Level II design simulation performance is compared directly (over-laid) to Level I performance.

Flow step number 4: Replace RF module with circuit schematics and keep accurate component/board models in place.

Flow step number 5: Replace RF module with data characterization models. Accurate simulation results from flow step number 4 are modeled in various forms (low-pass equivalent, extraction models depending on evaluation criteria), resulting in a very accurate RF module model (typically within five percent compared to Level III simulations) that is at least 100-times faster for simulation than Level III circuit simulations.

Finally, the RF Module of flow step number 5 is re-linked to the RF system and RF module design domains to close the final loop of bottom-up design regression validation.

Design concurrency and regression

The concept of “concurrent design” for IC silicon, IC package, PCB and prototype test development within the RF system design environment is a “must-do” requirement for meeting time-to-market demands and first-pass acceptable prototypes for today's RF systems.

The need for development of a concurrent design process is being driven by the demand for top-down design methodology for RF system, RF module and RFIC design, respectively. Further, the requirement exists to perform a final Golden Test Bench validation based on final design implementations, using a bottom-up regression design methodology at each design level: — RFIC-to-RF module, and later RF module-to-RF system.

Once system partitioning has been defined for boards and ICs, concurrent design, with iterative design refinement, should begin in conjunction with the top-down design flow shown in figure 2. Although design domains and tool database structures have been separate and independent entities in the past, market demands today require convergence and linkage.

The first steps for bringing together these design domains are the use of RF behavioral models functions using a common language, and provisions of various forms of data characterization model technologies (such as S-Parameters representing Field Solver analysis or extraction models), using measured or transistor-level simulated data from each design domain (such as IC, package, passive components, and board).

RF system and module design domains could be linked together effectively if the industry (design, test and EDA) would support and establish standards concerning the interaction of EDA design tools. Two important items to be standardized are a behavioral language (C/C++, VHDL, VHDL-AMS, Verilog, Verilog-A/AMS), and data characterization modeling formats (S-Parameter parameter or extracted into a C/C++ model).

Open Access (common database) is an important industry initiative that can further facilitate concurrent design for system, PCB and IC design domains.

What's feasible today and possible for tomorrow?

Design technologies available today include:

Behavioral models;

Extraction modeling techniques;

Data characterization models — sometimes referred to as table-based modeling; and

S-Parameters for discrete components and EM Field Solver parasitic effects.

All are available today within various EDA design tool environments, but not necessarily bi-directionally linked between design domains (such as PCB design to IC design).

Two other technologies that could be critical for the future for each design domain (System, IC, and PCB) are design-constrained (physical and electrical) floor planning, and combined analysis capability for noise and cross-coupling analysis and Field Solver integration.

The existence of design-constrained floor planning for ICs and separate/independent noise analysis technologies (substrate noise analysis, parasitic coupling analysis) is common knowledge. Some of these technologies also apply to PCB 21/2 D and full 3-D Field Solver technologies. What's lacking is the integration of these technologies for use at the “early design evaluation/ analysis” stage of design, including system, module and IC.

Industry demands of EDA suppliers should drive the need for this early design evaluation/analysis capability. To perform this first-order analysis, it is usually sufficient to utilize 21/2 D Field Solver and physical media input data; cross-section thickness, dielectric constants and conductivities for noise and parasitic coupling analyses.

Without the early design evaluation/analysis technologies, at best approximately 30 percent of field, noise and parasitic effects on the overall RF system and RF module design can be estimated.

Conclusion

EDA tools offer the capability to fully model, design and simulate an RF module, with some limitations and dedicated development of behavioral models. This existing capability can greatly reduce the very expensive risk of RFIC photo mask and silicon respins. However, system, board and IC design domains are not sufficiently interfaced to support a seamless, fully integrated top-down design environment. In addition, TTM requirements are forcing the need for RF system, module and IC designers to have readily available libraries for behavioral models, RF passives, and extraction models. When early design analysis technologies of design constrained floor planning and cross-coupling and substrate analysis are integrated within these design domains, RF module design accuracy will be much more comprehensive and precise.