Follow Heuristic Guidelines To Make Surface-Mount PC-Board Footprints

Guideline 5: Use a 1:1 ratio for solderstencil openings for all pins/terminal pads, except any exposed heatsink pads or other large apertures. For large apertures (3 by 3 mm and greater), shrink the periphery of the aperture by 0.25 mm to allow sufficient clearance between the large pad and surrounding pin/terminal pads, and break the large pad's aperture into multiple "window panes."

For the terminal pads, the task is automatically accomplished if the PCB-layout software is reset from the "cream" option to "on" for the terminal pads that were created. This creates a 1:1 aperture for each terminal pad's stencil layer—a value that works very well for both fine-pitch and standard-pitch leads when using a 6-mil thick stencil.

For the exposed pad polygon, however, you will need to create the pattern manually. Start by turning on both the top-copper layer (so you can see the polygon) and the stencil layer, where you will draw the corresponding aperture. Next, choose the rectangle function in your PCB-layout software, and create a set of window-pane apertures within the area of the polygon. (Make sure that you're placing these rectangles on electronic assembly the stencil layer.) Figure 5 shows the finished stencil openings for the package overlaid on the top-copper pattern.

Note how the exposed pad stencil openings are pulled away (inward) from the perimeter of the polygon, and especially from the corners. This reduces the likelihood of excess solder and resulting solder shorts.

Top Silkscreen: The top silkscreen carries the human-interface information you wish to appear on top of the PCB. This silkscreen doesn't serve any circuit function, but it is important to prototyping. It will help orient and place components during board assembly and assist in testing and debugging the prototype.

Conventionally, the silkscreen consists of the component-name layer, place layer, and value layer. The component-name layer supplies the IDs for the part on the board—for example, U1, R1, C5, and Q2. The value layer would include any associated values for the component— for example, 1k or 0.01 F. And, the place layer contains an outline and orientation for the component. We'll consider the top-place layer as the minimum requirement for the device.

Guideline 6: Use minimum 7-mil (0.007-in.) line widths for silkscreen features. Change the font type to "vector" and adjust the ratio and size as required to create readable letters and numbers.

Don't be tempted to place numbers by every pin, but do label pin 1 on SOICs. On QFN packages, it's helpful to have the silkscreen note the corner "pin" numbers. Make the top-stop layer visible while drawing on the topplace layer. Be careful not to place the silkscreen numbers/letters/lines too close to the solder-mask-stop apertures. Otherwise, the ink will bleed over into the associated depressions in the solder mask on the finished PCB.

Adjust the font's ratio and size to achieve the most readable text while maintaining the minimum line width. It's also helpful to place an outline around the part perimeter. Figure 6 shows the minimum silkscreen content for the example device, with the soldermask-stop layer shown for reference.

By closely following these steps, you can create any PCB layout package footprint you need. The result is a PCB footprint that, while not optimized for production, is robust for prototype PCB applications. In particular, the achievable goal is to substitute schematic-capture software for "napkin sketches" and quick-turn PCBs with electronic assembly solder stencils in place of hand-wired breadboards, while maintaining a rapid concept-to-labwork cycle that supports the engineer's creative process.