PCB Design and Layout

5.3 Reference planes

Due to their intrinsic reactance and resonances, tracks, wires, “star grounding”, area fills, guard rings, etc., cannot provide an adequate reference for a PCB except at low frequencies (usually below 1MHz). For example, the rule-of-thumb for the inductance of PCB tracks on their own or single wires, is 1nH/mm. This means that just 10mm of PCB track has an impedance of 6.3 Ω at 100MHz, and 63Ω at 1GHz. For this reason, only unbroken areas of metal conductor can provide an adequate reference up to 1GHz (and beyond), and these are called reference planes. In a PCB these are usually called power, ground, or 0V planes, but it is best to avoid the use of the words “ground” or “earth” in connection with EMC and circuits (reserving them for specific uses associated with safety bonding). As far as most EMC design techniques are concerned, a connection to the green/yellow protective earth conductor can often be more of a problem than a solution.

Reference plane techniques allow dramatic reductions in all unwanted EM coupling when used in conjunction with the other techniques described here. Reference planes are also essential for almost every other PCB EMC design technique to function properly.

5.3.1 Creating proper reference planes

A high-quality high-frequency reference must have a vanishingly small partial inductance, and can be created on a PCB by devoting one layer to an unbroken copper sheet, called a reference plane. A 0V reference plane would be used as the 0V (or “ground”) connection for all its associated circuits, so that all 0V return currents flow in the plane and not in tracks. Power planes are created and used in a similar manner for power connections and their return currents.

0V reference planes must lie under all their PCB Assembly components and all their associated tracks, and extend a significant distance way beyond them. The segregation and interface suppression techniques described above must still be followed even where a common 0V plane is used for a number of circuit areas.

Perforations such as leads, pins, and via holes increase the inductance of a plane, making it less effective at higher frequencies. “Buried via” techniques have been developed for cellphones, allowing interconnections between tracking layers without perforating the reference plane. For less demanding products a rule-of-thumb is that any gaps must have dimensions of 0.01λ or less at the maximum frequency concerned. For a good plane at 1GHz, (e.g. to help meet most of the present EU harmonised EMC standards cost-effectively) this rule implies that plane gaps should have dimensions ? 1.5mm (remembering that the velocity of propagation in FR4 is approx. half of what it is in air). "Sneaking" tracks into a plane layer is not allowed.

Unavoidable gaps in a plane must not merge to create larger ones. PCB design rules should size clearance holes so that for regular hole spacings such as DIL packages, the plane "webs" between holes as shown by Figure 5B.

Tracks, area fills, guard rings, etc. forming part of the reference on signal layers can be used to good effect at high frequencies – but only when bonded to an underlying 0V plane with at least one via hole every 5 to15mm (using a random allocation of spacings).

0V planes should extend well beyond all components, tracks and power planes. [1] recommends “the 20H rule”: 0V planes should extend by at least 20 times their layer spacing. High-speed components (such as digital clocks, processors, and memory) and their signal tracks should always be placed near the centres of their segregated areas, well away from plane edges.

All 0V and power connections must bond immediately to their respective planes to minimise their connection inductance. Leaded components must have their through-plated holes directly connected to planes using thermal-break pads as shown by figure 5B (sometimes called wagon-wheels) to help with soldering. Surface mounted devices (SMDs) for reflow soldering have to compromise the prevention of dry joints or “tomb-stoning” with the need to minimise inductance of plane connections.

Figure 5C shows various methods for connecting reflow-soldered SMDs to planes. Best is to use over-sized pads, tenting the solder-resist over a number of plane vias. Plane connections that do not need to be soldered (typical of the vias for reflow-soldered SMD components) may not need to use thermal-break pads – and using solid plane connections instead will reduce inductance.

Tracks, area fills, guard rings, etc. forming part of the reference on signal layers can be used to good effect at high frequencies – but only when bonded to an underlying 0V plane with at least one via hole every 5 to15mm (using a random allocation of spacings).

0V planes should extend well beyond all components, tracks and power planes. [1] recommends “the 20H rule”: 0V planes should extend by at least 20 times their layer spacing. High-speed components (such as digital clocks, processors, and memory) and their signal tracks should always be placed near the centres of their segregated areas, well away from plane edges.

All 0V and power connections must bond immediately to their respective planes to minimise their connection inductance. Leaded components must have their through-plated holes directly connected to planes using thermal-break pads as shown by figure 5B (sometimes called wagon-wheels) to help with soldering. Surface mounted devices (SMDs) for reflow soldering have to compromise the prevention of dry joints or “tomb-stoning” with the need to minimise inductance of plane connections.

Figure 5C shows various methods for connecting reflow-soldered SMDs to planes. Best is to use over-sized pads, tenting the solder-resist over a number of plane vias. Plane connections that do not need to be soldered (typical of the vias for reflow-soldered SMD components) may not need to use thermal-break pads – and using solid plane connections instead will reduce inductance.

5.3.6 Galvanically isolated planes

The split planes described above are all ultimately powered from the same power rails (0V, at least), so there is a clear need for return current paths to be catered for every conductor (signal or power) that crosses from one plane area to another. It is often assumed that galvanically isolated areas have no return current requirements, but this is not so at high frequencies.

Galvanic isolation devices (opto-isolators, transformers, etc.) suffer from stray internal capacitance. A typical opto has 0.8pF internal capacitance, which provides a shunting impedance of only 2kΩ at 100MHz, or 200Ω at 1GHz, which will clearly prevent signal isolation from being maintained at high frequencies. Transformers (especially in DC/DC power converters) tend to have even larger stray internal capacitances. Common-mode chokes may be used to improve the isolation at high frequencies, but struggle to increase it by an order of magnitude at 1GHz. There are also many other stray capacitances around to compromise isolation. So there is a need, at high frequencies, to provide a local return path for the displacement currents that flow in these stray capacitances, to prevent them from causing common-mode conducted and radiated emissions and immunity problems.

Because we usually only need isolation for low frequencies (usually only 50Hz) we can connect galvanically isolated planes to the main reference plane with a number of low-value capacitors (spread around the gap perimeter), so electronic assembly as to achieve the effect of a single reference plane for high frequencies and provide low-inductance local return paths for stray displacement currents.

Of course, great care may need to be taken with component approvals and leakage currents where safety is concerned.